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RTL Design Engineer

Poziții disponibile: 2 poziții
226
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FULL-TIME
Inginerie & Informație tehnologică
Oradea
Allengra Applied Technologies

   Job Description

   - RTL design using VHDL, Verilog, or SystemVerilog

   - Design of state machines, data paths, arbitration and clock domain crossing, sensor signal scanning logic

   - Logic synthesis, timing constraints

   - Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL

   - Synthesis and electrical rule checking Equivalence checking

   - Prior experience with Asynchronous Design

RTL Design Engineer
Allengra Applied Technologies
  • Oradea

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