Design Verification Engineer

Position details

Job Type: Full-time
Employment Type: Permanent
Start date: ASAP
Number of positions: 3

Summary

We’re in a business where building a better future is the goal. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, explore the opportunities available and come join our team.

Job requirements:

·         Desirable candidates have an BS degree in Computer Science / Applied Electronics, Micro-, opto- and nano-technologies and 2+ years of experience

·         Strong understanding of computer architecture

·         Strong knowledge of object-oriented programming languages (SystemVerilog or C++)

·         Strong debugging skills

·         Directed test-bench programming and creating of self-checking test-benches

Nice to have:

·         Knowledge of verification methodologies like UVM

·         Direct experience with Verilog simulators

·         Assembly programming

·         Experience in Mixed Signal verification

·         Constrained-random stimulus generation

Personal Competences:

·         Analytical thinking

·         Goal oriented (maintaining focus on agreed objectives and deliverables whatever the circumstances)

·         Good communication skills, the capacity to work within a team

·         Individual responsibility and a strong desire for personal achievements

·         Should have the desire to evolve towards a very good professional & technical level

·         Very good knowledge of English

Expected tasks:

·         Perform functional feature verification of high-speed Microprocessor designs

·         Defining, developing and executing test/coverage plans at unit and system level

·         Based on thorough understanding of the design architecture, develop, run and debug directed tests, random exercisers and the needed infrastructure to validate functionality (Checkers/Monitors/etc.)

·         UVM/C++ based testbench development

·         SystemVerilog/X86 Assembly test development

·         Debugging designs in Verilog and SystemVerilog

·         Verification flow enhancements using a scripting language

Benefits:

·         Competitive salary

·         Flexible working schedule

·         Challenging and professional work environment within a global organization

·         Opportunity to work for/with international top companies

·         Subscription for medical services at a private health center in Iasi