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SENIOR DFT DESIGN FOR TEST ENGINEER - REMOTE

Poziții disponibile: 10 poziții
85
0
FULL-TIME
Auto & Automotive
Brașov
CAPGEMINI ENGINEERING

Our offer

  • Competitive Salary & Benefits;
  • Knowledge and support from more experienced engineers;
  • Respect for your private life and your choices;
  • All tools required for high performance in your field;
  • Responsible approach, long term commitments, and stability;
  • Relocation Package for non-Cluj residents.

Your role

  • provide SOC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements;
  • perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation;
  • verify DFT circuitry and interface with other blocks, debug timing simulation issues.

Your profile

  • Sound basics of DFT aspects of scan DRC, ATPG DRC and simulation debug skills;
  • Basic knowledge of compression structure and MBIST structure of any EDA tools;
  • Usage of simulation and waveform viewer tool flow from any debugging tools from Synopsys, Mentor or Cadence;
  • Good knowledge of Perl/TCL/Python scripting;
  • Expertise with Synopsys EDA tools such as SMS, compression architecture of same.
SENIOR DFT DESIGN FOR TEST ENGINEER - REMOTE
CAPGEMINI ENGINEERING

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