Digital Hardware Verification Manager

We are seeking a highly motivated and innovative manager, with background in high-speed protocols and the wish to grow on protocol knowledge by verification related work.

You will work with the Site Manager in Romania to scale a world class team in Bucharest and will be part of Solutions Group Business Unit (SG), developing IPs for DesignWare IPs.


Your Key responsibilities:

• Grow a high functioning team responsible for the verification of RTL designs
• Select, develop and evaluate staff to ensure quality output
• Regular interactions with customers on product requirements
• Prepare and presents reports on technical projects
• Drive innovation culture within the team
• Deliver overall solution for verifying the protocol of an interface standard

Key responsibilities of your team:

• Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
• Generate verification test plan, verification environment documentation and test environment usage documentation
• Define, develop, and verify complex UVM verification environments
• Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioural modelling, and verification coverage metrics (functional coverage and code coverage)
• Identify design problems, possible corrective actions and/or inconsistencies on documented functionality

 Your Key Qualifications

• Be a role model for those within the team and be operating at a pro level
• Good understanding of what it takes to develop and deliver best in class verification
• Be organized and have good judgement
• Proficient in Romanian and English

Key Qualifications of your team

• Proven desire to learn and explore new state of the art technologies
• Demonstrate good written and spoken English communication skills
• Demonstrate good review and problem-solving skills
• Knowledgeable with Verilog, VHDL and/or SystemVerilog
• Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus
• Understanding of verification methodology such as UVM is a plus
• Good organization and communication skills
• 4+ years of relevant experience

Your Preferred Experience 

• 10+ years of experience in design verification with 4 years in a management role
• Deep understanding of UVM concepts and System Verilog

What we offer

• Attractive salary with a regular bonus, and other exciting incentives based on seniority
• Work on state-of-the-art products, using cutting edge technologies
• Stable and supportive work environment: we value integrity, execution excellence, passion and trust
• Outstanding professional growth opportunities: the R&D Center of Synopsys in Bucharest will be growing dramatically over the next years
• Work with exceptional talent around the world
• Good health benefits as standard

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with tools and Interface IP solutions.

If you share our passion for innovation and value creation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.